Shallow source/drain extension effects on external resistance in sub-0.1 μm MOSFETs

Accurate external resistance extraction for shallow source/drain extension (SDE) MOSFET´s is demonstrated using a unified mobility model for inversion and accumulation layers. The parasitic resistance in the accumulation layer (R_acc) is highly dependent both on the SDE junction depth (X_j) and the gate overlap length (L_ou ). Due to the laterally finite doping gradient, R_acc becomes dominant among other external resistance components in sub-0.1 μm MOSFETs. Hence, device optimization to minimize R_acc is necessary in order to improve on-current and SDE to the gate coupling. A NMOS transistor with L_eff of 0.08 μm shows a maximum on-current while maintaining a lower off-leakage current for a L_ou of 20 nm and X_j of 40 nm