Title :
Implementation of QRD-RLS algorithm on FPGA. Application to Noise Canceller System
Author :
Martinez, M.E.I.
Author_Institution :
Centro de Desarrollo de la Electron. y la Autom. (CDEA), Pinar del Rio, Cuba
fDate :
7/1/2011 12:00:00 AM
Abstract :
This article describes one of the many applications of adaptive filtering algorithms, in this case the noise reduction or cancellation in particular using the QRD-RLS algorithm, conducting its implementation on FPGA and taking as the cornerstone of the work, the flexibility of these devices and the advantages of hardware acceleration algorithms in certain applications.
Keywords :
field programmable gate arrays; FPGA; QRD-RLS algorithm; adaptive filtering algorithm; cancellation; hardware acceleration algorithm; noise canceller system; noise reduction; Adaptation models; Digital signal processing; Field programmable gate arrays; Generators; Hardware; Hardware design languages; Mathematical model; FPGA; QRD-RLS; algorithm;
Journal_Title :
Latin America Transactions, IEEE (Revista IEEE America Latina)
DOI :
10.1109/TLA.2011.5993728