Title :
Post-silicon Validation Procedure for a PWL ASIC Microprocessor Architecture
Author :
Lifschitz, Omar ; Rodriguez, J.A. ; Julian, Pedro ; Agamennoni, O.
fDate :
7/1/2011 12:00:00 AM
Abstract :
In this paper, we present the environment set for validation and testing a particular ASIC that implements a piecewise linear (PWL) architecture. Description for a package debug propose is included. Methodologies for power consumption and maximum operation frequency estimation, based on laboratory measurements, are described.
Keywords :
application specific integrated circuits; integrated circuit testing; PWL ASIC microprocessor architecture; laboratory measurement; maximum operation frequency estimation; package debug propose; piecewise linear architecture; post-silicon validation; power consumption; Application specific integrated circuits; Clocks; Computer architecture; Discrete Fourier transforms; Field programmable gate arrays; Microprocessors; Read only memory; ASIC; Piecewise linear; Validation;
Journal_Title :
Latin America Transactions, IEEE (Revista IEEE America Latina)
DOI :
10.1109/TLA.2011.5993733
