DocumentCode
1304021
Title
Post-silicon Validation Procedure for a PWL ASIC Microprocessor Architecture
Author
Lifschitz, Omar ; Rodriguez, J.A. ; Julian, Pedro ; Agamennoni, O.
Volume
9
Issue
4
fYear
2011
fDate
7/1/2011 12:00:00 AM
Firstpage
492
Lastpage
497
Abstract
In this paper, we present the environment set for validation and testing a particular ASIC that implements a piecewise linear (PWL) architecture. Description for a package debug propose is included. Methodologies for power consumption and maximum operation frequency estimation, based on laboratory measurements, are described.
Keywords
application specific integrated circuits; integrated circuit testing; PWL ASIC microprocessor architecture; laboratory measurement; maximum operation frequency estimation; package debug propose; piecewise linear architecture; post-silicon validation; power consumption; Application specific integrated circuits; Clocks; Computer architecture; Discrete Fourier transforms; Field programmable gate arrays; Microprocessors; Read only memory; ASIC; Piecewise linear; Validation;
fLanguage
English
Journal_Title
Latin America Transactions, IEEE (Revista IEEE America Latina)
Publisher
ieee
ISSN
1548-0992
Type
jour
DOI
10.1109/TLA.2011.5993733
Filename
5993733
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