DocumentCode :
1304510
Title :
The Truga001: a scalable rendering processor
Author :
Ikedo, Tsuneo ; Ma, Jianhua
Author_Institution :
Sch. of Inf. Syst., Aizu Univ., Japan
Volume :
18
Issue :
2
fYear :
1998
Firstpage :
59
Lastpage :
79
Abstract :
To support the increasing interest in virtual reality systems, computer graphics must now be extremely powerful to obtain realistic images. VR systems are based on two technical tools: graphics accelerators and pixel renderers. The paper discusses the Truga001 single-chip rendering processor for virtual reality and multimedia systems. It embeds 12 graphics processors and 7 special modules in a single chip
Keywords :
application specific integrated circuits; microprocessor chips; multimedia computing; realistic images; rendering (computer graphics); virtual reality; ASIC; Truga001; application specific integrated circuit; computer graphics; graphics accelerators; graphics processors; multimedia systems; pixel renderers; realistic images; scalable rendering processor; single-chip rendering processor; virtual reality; Computer graphics; Delay; Eyes; Geometry; Hardware; Layout; Protocols; Rendering (computer graphics); Virtual reality; Visualization;
fLanguage :
English
Journal_Title :
Computer Graphics and Applications, IEEE
Publisher :
ieee
ISSN :
0272-1716
Type :
jour
DOI :
10.1109/38.656790
Filename :
656790
Link To Document :
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