Title :
Reliability Screening of a-Si TFT Circuits: Very-Low Voltage and
Testing
Author :
Shen, Shiue-Tsung ; Liu, Chester ; Ma, En-Hua ; Cheng, I-Chun ; Li, James Chien-Mo
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
This paper compares very-low-voltage (VLV) testing and quiescent power supply current (IDDQ) testing for amorphous silicon thin-film transistor (a-Si TFT) NMOS digital circuits. As many as 140 circuits-under-test (CUT) of two different design styles are implemented in 8 μm a-Si TFT technology on the glass substrate. All CUT are tested both at nominal voltage (10 V) and very low voltage (7 V), followed by a 200-second voltage stress at 30 V. Seven unreliable CUT that escaped nominal voltage (NV) testing are successfully caught by VLV testing. The results indicate that VLV testing is more effective than IDDQ testing to screen out unreliable a-Si TFT circuits. This study suggests that VLV testing is a non-destructive and economic alternative to burn-in for a-Si TFT circuits.
Keywords :
MOS digital integrated circuits; amorphous semiconductors; elemental semiconductors; integrated circuit reliability; integrated circuit testing; silicon; thin film transistors; IDDQ testing; Si; SiO2; a-Si TFT circuits; amorphous silicon thin-film transistor NMOS digital circuits; circuits-under-test; glass substrate; quiescent power supply current testing; reliability screening; size 8 mum; very-low-voltage testing; voltage 10 V; voltage 30 V; Delay; Logic gates; Reliability; Stress; Testing; Thin film transistors; $({rm I}_{rm DDQ})$ testing; Amorphous silicon thin-film transistor (a-Si-TFT); reliability; very-low voltage (VLV) testing;
Journal_Title :
Display Technology, Journal of
DOI :
10.1109/JDT.2010.2060469