Title :
Integrated circuits for a real-time large-vocabulary continuous speech recognition system
Author :
Stölzle, Anton ; Narayanaswamy, Shankar ; Murveit, Hy ; Rabaey, Jan M. ; Brodersen, Robert W.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
1/1/1991 12:00:00 AM
Abstract :
The architecture and implementation of a word processing subsystem for a real-time speech recognition system using hidden Markov models are described. The bottleneck of this system, which is the acquisition of data, is demonstrated, and an architecture that speeds up this bottleneck using on-chip dual-ported cache memories is presented. The architecture is described in a textual form, and the layout data were completely automatically generated. The chips have been fabricated through MOSIS using a 2-μm CMOS n-well technology. The functionality of the processors was successfully tested using the scan-path test methodology. The clock rate for the scan-path test was 5 MHz to guarantee proper operation of the circuits for this clock rate. All the processors were first time working silicon
Keywords :
CMOS integrated circuits; Markov processes; computer architecture; computerised signal processing; digital signal processing chips; real-time systems; signal processing equipment; speech recognition; 2 micron; 5 MHz; CMOS n-well technology; MOSIS; Si; Viterbi processor; clock rate; hidden Markov models; on-chip cache memories; on-chip dual-ported cache memories; pipelining; predecessor processing; probability; real-time large-vocabulary continuous speech recognition; scan-path test; successor processing; word processing subsystem; CMOS technology; Cache memory; Circuit testing; Clocks; Hidden Markov models; Real time systems; Silicon; Speech recognition; System-on-a-chip; Text processing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
