Variable bit organization as a new test function for standard memories

Author

Wada, Tomohisa ; Eino, Masanao ; Ukita, Motomu ; Anami, Kenji

Author_Institution

Mitsubishi Electr. Corp., Itami, Japan

Volume

26

Issue

1

fYear

1991

fDate

1/1/1991 12:00:00 AM

Firstpage

51

Lastpage

54

Abstract

A variable bit-organization function that enables the RAM to be used in plural bit organizations is proposed. This function reduces the test time for many kinds of test patterns and data patterns. Consequently, a short-time, accurate, and severe test is realized. This test-time reduction function is important in a high-speed memory such as SRAM because it preserves the same access time for the different organizations. Using the output driver transistor as the input protection circuit, a low and uniform input/output pin capacitance of 3.5 pF and a high electrostatic discharge (ESD) immunity have also been realized. This function has been successfully implemented in a 1-Mb SRAM configurable for both 1-M-word×1-b and 256K-word×4-b organizations without any practical drawbacks

Keywords

SRAM chips; integrated circuit testing; memory architecture; 1 MB; 3.5 pF; RAM; SRAM; data patterns; electrostatic discharge; input protection circuit; output driver transistor; plural bit organizations; standard memories; test patterns; test-time reduction function; variable bit-organization function; Automatic testing; Capacitance; Circuit testing; Electrostatic discharge; Protection; Random access memory; Read-write memory; Standards organizations; Time measurement; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.65709

Filename

65709