Title :
Design of fault-diagnosable and repairable folded PLAs for yield enhancement
Author :
Wey, Chin-Long ; Chang, Tsin-Yuan ; Ding, Jyhyeuan
Author_Institution :
Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
fDate :
1/1/1991 12:00:00 AM
Abstract :
A defect-tolerant PLA (programmable logic array) design with a simple column folding technique to enhance the probe yield is presented. The results show that the design requires less die size than a previous design, while still achieving full diagnosability of single and multiple stuck-at, bridging, and crosspoint faults. The design concept is readily extended to other folding techniques. Among the various folding techniques, the trade-offs are the density improvement and regularity, i.e. the density improvement is often paid for as higher irregularity. In fact, the irregularity often results in a higher defect density. It is concluded that a density improvement does not guarantee a higher overall yield
Keywords :
fault location; fault tolerant computing; logic arrays; logic design; bridging; column folding; crosspoint faults; defect-tolerant PLA; density; diagnosability; die size; logic design; probe yield; programmable logic array; regularity; repairable PLA; stuck at fault; yield enhancement; Circuit faults; Circuit testing; Fault tolerance; Integrated circuit yield; Logic design; Manufacturing processes; Probes; Programmable logic arrays; Ultra large scale integration; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of