Title :
Design of CMOS circuits for stuck-open fault testability
Author :
Jayasumana, Anura P. ; Malaiya, Yashwant K. ; Rajsuman, Rochit
Author_Institution :
Colorado State Univ., Fort Collins, CO, USA
fDate :
1/1/1991 12:00:00 AM
Abstract :
A CMOS design that offers highly testable CMOS circuits is presented. The design requires a minimal amount of extra hardware for testing. The test phase for the proposed design is simple and uses a single test vector to detect a fault. The design offers the detection of transistor stuck-open faults deterministically. In this design, the tests are not invalidated due to timing skews/delays, glitches, or charge redistribution among the internal nodes
Keywords :
CMOS integrated circuits; fault location; integrated logic circuits; logic design; logic testing; CMOS design; charge redistribution; glitches; internal nodes; logic design; logic testing; single test vector; stuck-open fault testability; timing skews/delays; transistor; Circuit faults; Circuit testing; Electrical fault detection; FETs; Fault detection; Hardware; Helium; Logic testing; Robustness; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
