Modeling the wiring of deep submicron ICs

The semiconductor industry has fuelled the enormous growth of the electronics industry with an unending flow of even better, faster, cheaper chips. These chip improvements, in turn, have been stoked by steady progress in semiconductor process technology, which, as Moore´s law predicts, doubles IC transistor counts every 18 months. Supporting this progress is the infrastructure provided by design tools, which today, however, comes up short against the process advances crucial to tomorrow´s chips. Why? Because present design tools and methodologies presuppose that chip performance is determined by the transistor. That supposition may have been true a few years ago, but no more. Chip performance now depends on the interconnect. The new significance of interconnect performance is driving changes throughout the logic design flow because logic synthesis engines and other tools assume that timing can be predicted before the physical layout is done. But pre-layout and post-layout timing values no longer converge, and design tools must evolve to match this change in process technology. The first step is for vendors to create tools that accurately predict the performance of designs in this interconnect-dominated technology. The author discusses the importance of timing, 2D and 3D modelling of the interconnects, and deep submicron effects