Design for testability using behavioral models

A systematic approach to analog design-for-testability is presented. This approach uses behavioral models for fault simulation so that objective comparisons can be made between alternative test configurations. Design tradeoffs involved in circuit positioning are discussed. Its suitability for use with application-specific integrated circuit (ASIC) design strategies is demonstrated. This technique is especially well suited to an ASIC environment because the models can be reused and combined to form a library. The fault models should improve with time as more data is collected for a given block. The behavioral models can also be used to decide what specifications a block will need to function properly in a given system, which is very useful in the design phase for determining how well blocks will fit together or how much linearity or signal swing a given block will need to achieve a certain high-level system specification