Characterizing the Capacitive Crosstalk in SRAM Cells Using Negative Bit-Line Voltage Stress

The physical distance between adjacent memory cells is rapidly decreasing as memory density increases and technology geometry shrinks. As a result of the narrower distance, the capacitance between adjacent cells, which are referred to as the cell coupling capacitor (C_CCP), increases and behaves as the source of crosstalk. The crosstalk is further aggravated by increasing operational speeds. When the sizes of the C_CCP are marginal, they may not be detected by normal test patterns but can appear when various stresses accumulate. When they are not detected in an early manufacturing stage, they become the source of intermittent failures. Creating a complex test environment is sometimes rejected at the expense of higher parts per million of a device. In this paper, a negative voltage stress is applied to bit lines to test and diagnose the issues from the marginal C_CCP. The negative voltage level is closely correlated to the C_CCP size, which implies that the proposed method can be used as a vehicle to diagnose the potential issues due to cell coupling capacitors. The simulation results demonstrated that the negative stress voltage can screen the cell coupling capacitors from a few femtofarads to tens of femtofarads in an experimental circuit. The proposed technique has been validated by test chip using 130-nm technology.