A 60-GHz SPST switch in 65-nm CMOS technology

Author

Alit Apriyana, Anak Agung ; Yue Ping Zhang

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore

fYear

2014

fDate

27-30 Aug. 2014

Firstpage

1

Lastpage

3

Abstract

An enhanced circuit model is developed for a 60-GHz single-pole single-throw (SPST) switch in 65nm CMOS technology in this paper. The enhanced circuit model involves the modeling of the drain-to-source parasitic capacitances that are introduced by the overlapped multi-finger drain-to-source metallization of the transistors and also the modeling the distributive and coupling effect of lines interconnection, testing pads and ground metals. The enhanced circuit model leads to an improved agreement between the simulated and measured performance over the frequency range from 1 to 170 GHz.

Keywords

CMOS integrated circuits; integrated circuit metallisation; integrated circuit modelling; microwave switches; CMOS technology; SPST switch; coupling effect; drain-to-source parasitic capacitances; enhanced circuit model; frequency 1 GHz to 170 GHz; frequency 60 GHz; ground metals; multi-finger drain-to-source metallization; single-pole single-throw switch; size 65 nm; CMOS integrated circuits; Capacitance; Integrated circuit modeling; Ports (Computers); Semiconductor device modeling; Switching circuits; Transistors; 60-GHz radio; LTCC; microstrip grid array antenna;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio-Frequency Integration Technology (RFIT), 2014 IEEE International Symposium on

Conference_Location

Hefei

Type

conf

DOI

10.1109/RFIT.2014.6933242

Filename

6933242