Non-binary SAR ADC with a two-mode comparator

In this paper, a 10b SAR ADC is designed for low power and low speed application. A two-mode comparator is applied on a generalized non-binary algorithm for better power efficiency. The comparator works in the low accuracy mode during the first few steps, and works in the high accuracy mode for the last few steps. Compared to a conventional SAR ADC, which has a high-accuracy comparator to complete all the comparison steps, worsened static performance would be resulted by such an approach. Therefore, a generalized non-binary algorithm with error correction ability is applied and the capacitance values of the DAC array were adjusted to achieve better static performance. A non-binary SAR ADC with the conventional structure is also constructed for performance comparison. Both SAR ADCs were designed and simulated using GF 40nm technology. The simulation results show that with comparable static performance, the non-binary ADC with a two-mode comparator shows better power efficiency.