Analyzing the nonlinearity of binary phase detector in phase-locked loops

Clock Data Recovery (CDR) circuits based on binary phase detector gained popularity in the last decade. In this paper, nonlinear control theory, specifically describing function, is employed to analyze the stability of PLL circuits for both ideal binary phase detector (BPD) and BPD with consideration of metastability. The significance of loop delay and metastability are discussed. The derived results can be used to guide the loop design.