• DocumentCode
    1305647
  • Title

    A genetic algorithm framework for test generation

  • Author

    Rudnick, Elizabeth M. ; Patel, Janak H. ; Greenstein, Gary S. ; Niermann, Thomas M.

  • Author_Institution
    Center for Reliable & High Performance Comput., Illinois Univ., Chicago, IL, USA
  • Volume
    16
  • Issue
    9
  • fYear
    1997
  • fDate
    9/1/1997 12:00:00 AM
  • Firstpage
    1034
  • Lastpage
    1044
  • Abstract
    Test generation using deterministic fault-oriented algorithms is highly complex and time consuming. New approaches are needed to augment the existing techniques, both to reduce execution time and to improve fault coverage. Genetic algorithms (GA´s) have been effective in solving many search and optimization problems. Since test generation is a search process over a large vector space, it is an ideal candidate for GA´s. In this work, we describe a GA framework for sequential circuit test generation. The GA evolves candidate test vectors and sequences, using a fault simulator to compute the fitness of each candidate test. Various GA parameters are studied, including alphabet size, fitness function, generation gap, population size, and mutation rate, as well as selection and crossover schemes. High fault coverages were obtained for most of the ISCAS´89 sequential benchmark circuits, and execution times were significantly lower than in a deterministic test generator in most cases
  • Keywords
    automatic testing; fault diagnosis; genetic algorithms; integrated circuit testing; logic testing; sequential circuits; ISCAS´89 sequential benchmark circuits; alphabet size; crossover schemes; deterministic fault-oriented algorithms; execution time; fault coverage; fault coverages; fault simulator; fitness function; generation gap; genetic algorithm framework; mutation rate; population size; search process; selection schemes; test generation; test vectors; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Fault detection; Genetic algorithms; Logic testing; Sequential analysis; Sequential circuits;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.658571
  • Filename
    658571