DocumentCode
1305809
Title
A new erasing method for a single-voltage long-endurance flash memory
Author
Bez, R. ; Cantarelli, D. ; Moioli, L. ; Ortolani, G. ; Servalli, G. ; Villa, C. ; Dallabora, M.
Author_Institution
SGS-Thomson Microelectron., Agrate Brianza, Italy
Volume
19
Issue
2
fYear
1998
Firstpage
37
Lastpage
39
Abstract
A new method to erase a standard (double-poly, stacked-gate NOR-type) flash cell is proposed. The method, still using the tunneling mechanism to extract electrons from the floating gate, is based on the concept of keeping the electric field constant during the whole erasing operation. The new method has two main advantages with respect to the conventional one: (1) it does not depend on the supply voltage variation and (2) it allows a better reliability in terms of endurance-induced stress. Results have shown that flash device performances are greatly improved in terms of stability and endurance reliability up to one million cycles.
Keywords
circuit stability; integrated circuit reliability; integrated circuit testing; integrated memory circuits; tunnelling; 4 Mbit; constant electric field; double-poly stacked-gate NOR-type flash cell; electron extraction; endurance-induced stress; erasing method; floating gate; reliability; single-voltage long-endurance flash memory; stability; tunneling mechanism; Electrons; Energy barrier; Flash memory; Nonvolatile memory; Silicon; Stability; Stress; Tunneling; Voltage control;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.658595
Filename
658595
Link To Document