• DocumentCode
    1306494
  • Title

    Design of testable multipliers for fixed-width data paths

  • Author

    Mukherjee, Nilanjan ; Rajski, Janusz ; Tyszer, Jerzy

  • Author_Institution
    Eng. Res. Center, AT&T Bell Labs., Princeton, NJ, USA
  • Volume
    46
  • Issue
    7
  • fYear
    1997
  • fDate
    7/1/1997 12:00:00 AM
  • Firstpage
    795
  • Lastpage
    810
  • Abstract
    The usage of multipliers in fixed-width data-dominated architectures (also termed data paths) poses serious testability problems. Due to truncation of their outputs, the fault observability of the multipliers degrades, and the resulting output patterns are inadequate to completely test functional blocks that are driven by them. Consequently, the overall random pattern testability of data paths deteriorates substantially. In this paper, we propose new generic design schemes, based on residue number system arithmetic, to improve the overall testability of data paths. The approach uses, in the test mode, the truncated least significant bits of the product to increase the variety of patterns at the output of a multiplier. This, in turn, improves the fault detectability of multipliers, and consequently, have a remarkable impact on the overall testability of data paths. The proposed techniques can be incorporated with a minimal performance degradation and area overhead, and are independent of the multiplier architecture. Experimental analysis performed on four high-level synthesis benchmarks exhibits a significant improvement in the overall testability of the corresponding data-path implementations
  • Keywords
    built-in self test; design for testability; digital arithmetic; high level synthesis; multiplying circuits; residue number systems; fault detectability; fault observability; fixed-width data paths; fixed-width data-dominated architectures; functional blocks; generic design schemes; high-level synthesis benchmarks; random pattern testability; residue number system arithmetic; testable multipliers design; Arithmetic; Automatic testing; Benchmark testing; Circuit faults; Circuit synthesis; Circuit testing; Degradation; Design for testability; Fault detection; High level synthesis; Observability; Performance analysis; Performance evaluation; System testing;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.599900
  • Filename
    599900