Title :
Signed binary addition circuitry with inherent even parity outputs
Author_Institution :
Dept. of Comput. Syst. Eng., Arkansas Univ., Fayetteville, AR, USA
fDate :
7/1/1997 12:00:00 AM
Abstract :
A signed binary (SE) addition circuit is presented that always produces an even parity representation of the sum word. The novelty of this design is that no extra check bits are generated or used. The redundancy inherent in a SE representation is further exploited to contain parity information
Keywords :
adders; digital arithmetic; error detection; check bits; even parity representation; inherent even parity outputs; parity information; signed binary addition circuitry; Adders; Buildings; Circuits; Computer Society; Costs; Counting circuits; Delay; Digital arithmetic; Electrical fault detection; Logic circuits; Redundancy;
Journal_Title :
Computers, IEEE Transactions on
