Title :
BiCMOS circuit optimisation technique linking channel width of MOS device to collector design of BJT
Author :
Rofail, S.S. ; Seng, Y.K.
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore
fDate :
12/5/1996 12:00:00 AM
Abstract :
A methodology to optimise the propagation delay of BICMOS/BiNMOS circuits for high level injection is proposed. It is based on modifying the collector design of the BJT in association with an increase in the channel width of the MOS device to account for the speed degradation caused by the onset of high level injection. A sensitivity-type approach has been adopted to link the value of the channel width of the MOS device to the collector profile of the BJT
Keywords :
BiCMOS integrated circuits; circuit optimisation; integrated circuit design; BJT; BiCMOS circuit optimisation; BiNMOS circuit; MOS device; channel width; collector design; high level injection; propagation delay; sensitivity; speed;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19961544
