DocumentCode
1307285
Title
Design considerations for millimeter-wave power HBTs based on gain performance analysis
Author
Tanaka, Shin´ichi ; Amamiya, Yasushi ; Murakami, Seiichi ; Shimawaki, Hidenori ; Goto, Norio ; Takayama, Yoichiro ; Honjo, Kazuhiko
Author_Institution
Opto-Electron. & High Frequency Device Res. Labs., NEC Corp., Ibaraki, Japan
Volume
45
Issue
1
fYear
1998
fDate
1/1/1998 12:00:00 AM
Firstpage
36
Lastpage
44
Abstract
Critical design issues involved in optimizing millimeter-wave power HBTs are described. Gain analysis of common-emitter (CE) and common-base (CB) HBTs is performed using analytical formulas derived based on a practical HBT model. While CB HBT´s have superior maximum-gain at very high frequencies, their frequency limit is found to be determined by the carrier transit time delay. Thus, to fully exploit the potential gain in a CB HBT, it is essential to maintain a high fT even at high collector voltages. The advantage of using CB HBT´s in a multifingered device geometry is also discussed. Unlike CE HBTs, CB HBTs are capable of maintaining a high gain even if the device size is scaled up by increasing the number of emitter-fingers. Moreover, it is found that reducing the wire parasitic capacitance allows emitter ballasting resistance to be used without affecting the gain. Fabrication of HBTs based on these design considerations led to excellent power performance in a CB unit-cell HBT at 25-26 GHz, featuring output power of 740 mW and power-added efficiency of 42%
Keywords
capacitance; heterojunction bipolar transistors; millimetre wave bipolar transistors; millimetre wave power transistors; power bipolar transistors; semiconductor device models; 25 to 26 GHz; 42 percent; 740 mW; HBT model; carrier transit time delay; collector voltages; common-base configuration; common-emitter configuration; emitter ballasting resistance; emitter-fingers; frequency limit; gain performance analysis; millimeter-wave power HBT; multifingered device geometry; output power; power performance; power-added efficiency; wire parasitic capacitance; Delay effects; Design optimization; Frequency; Geometry; Heterojunction bipolar transistors; Parasitic capacitance; Performance analysis; Performance gain; Voltage; Wire;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.658809
Filename
658809
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