Improved circuit implementation of adaptive phase comparators

An improved implementation of an adaptive phase comparator circuit is presented. The adaptive phase comparator can be thought of as a five-cell up-down counter that is bounded in both the outermost cells. A new design concept leads to a circuit with a higher maximum operation frequency while maintaining the basic requirements of handling coincident input signals and absence of intermediate states. The circuit is based on the application of a number of identical logic elements, which are placed in a ring structure