Title :
Systolic band-matrix multipliers
Author_Institution :
Comput. Lab., Oxford Univ., UK
fDate :
3/15/1990 12:00:00 AM
Abstract :
Four methods for generating systolic band-matrix multipliers with different degrees of pipelining are presented. The tradeoffs in complexity and performance of the resulting designs are analysed.
Keywords :
VLSI; cellular arrays; digital integrated circuits; multiplying circuits; pipeline processing; complexity performance tradeoffs; degrees of pipelining; systolic band-matrix multipliers;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19900263
