On comparing hardware implementations of fixed point digital filters

Distributed arithmetic structures are an alternative to the use of conventional multipliers in hardware implementations of digital filters. The authors compare the various methods of using distributed arithmetic in implementing fixed point digital filters. They introduce as a measure of hardware complexity the chip area needed to fabricate competing designs using nMOS technology. Comparisons of alternate realizations in hardware are also made. These comparisons are based on equating the output signal quality of each design. They show that traditional measures of complexity (such as the number of multipliers per output sample) do not agree with complexity measures based on chip area.