DocumentCode
1309870
Title
SEU critical charge and sensitive area in a submicron CMOS technology
Author
Detcheverry, C. ; Dachs, C. ; Lorfevre, E. ; Sudre, C. ; Bruguier, G. ; Palau, J.M. ; Gasiot, J. ; Ecoffet, R.
Author_Institution
CEM2, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
Volume
44
Issue
6
fYear
1997
fDate
12/1/1997 12:00:00 AM
Firstpage
2266
Lastpage
2273
Abstract
This work presents SEU phenomena in advanced SRAM memory cells. Using mixed-mode simulation, the effects of scaling on the notions of sensitive area and critical charge is shown. Specifically, we quantify the influence of parasitic bipolar action in cells fabricated in a submicron technology
Keywords
CMOS memory circuits; SRAM chips; VLSI; cellular arrays; circuit analysis computing; integrated circuit reliability; integrated circuit testing; SEU critical charge; SEU sensitive area; SRAM memory cells; critical charge; mixed-mode simulation; parasitic bipolar action; sensitive area; submicron CMOS technology; CMOS technology; Circuit simulation; Inverters; Random access memory; SPICE; Semiconductor process modeling; Single event upset; Space technology; Switches; Voltage;
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/23.659045
Filename
659045
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