Title :
Newly structured expandable 52-Mbit/s, 48-channel time-division switching LSI with 2.4 Gbit/s throughput
Author :
Yamanaka, N. ; Kikuchi, Shinji
Author_Institution :
NTT Commun. Switching Labs., Tokyo, Japan
fDate :
4/14/1990 12:00:00 AM
Abstract :
An expandable Si bipolar 2.4 Gbit/s throughput, 52 Mbit/s 48-channel time-division switching LSI system is described. A high-throughput of 2.4 Gbit/s and a power-dissipation of 5.3 W are achieved by adopting a low-voltage swing four-serial-gated differential bipolar circuit design and super self-aligned process (SST-1A) logic-in-memory LSI technology. This LSI is applicable to the digital video time-division switching and digital crossconnect systems of future B-ISDN.
Keywords :
ISDN; bipolar integrated circuits; elemental semiconductors; integrated circuit technology; large scale integration; multiplexing equipment; silicon; time division multiplexing; 2.4 Gbit/s; 5.3 W; 52 Mbit/s; B-ISDN; LSI; SST process; Si chip; TDM; bipolar ICs; broadband ISDN; digital crossconnect systems; digital video time-division switching; expandable; four-serial-gated differential bipolar circuit design; logic-in-memory LSI technology; low-voltage swing; multichannel; power-dissipation; semiconductors; super self-aligned process; throughput; time-division switching;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19900341
