DocumentCode
1310020
Title
Benchmarking of III–V n-MOSFET Maturity and Feasibility for Future CMOS
Author
Doornbos, Gerben ; Passlack, Matthias
Author_Institution
Adv. Transistor Res. Div., TSMC Eur. BV, Leuven, Belgium
Volume
31
Issue
10
fYear
2010
Firstpage
1110
Lastpage
1112
Abstract
With the consideration of III-V channels for future CMOS, an urgent need for standard metrics to assess the maturity of III-V MOSFETs and to investigate their suitability for future CMOS has arisen. By proposing such standard metrics (Q ≡gm/S), we find that present InGaAs n-MOSFETs are trailing Si MOSFETs by over a factor of 30. Still, experimental PHEMT data make a clear case for the utilization of InAs channels in future CMOS from a performance standpoint both for HP (1.4-1.7 times the current drive increase over Si) and LOP (1.7-3 times) applications.
Keywords
CMOS integrated circuits; III-V semiconductors; MOSFET; benchmark testing; III-V channels; benchmarking; future CMOS; maturity; n-MOSFET; CMOS integrated circuits; Gallium arsenide; Indium gallium arsenide; Logic gates; MOSFETs; PHEMTs; Silicon; CMOS; MOSFET; PHEMT; QWFET; high- $kappa$ dielectrics; high-mobility channel;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2010.2063012
Filename
5560720
Link To Document