High-Performance Gate-Enhanced Power UMOSFET With Optimized Structure

An optimized gate-enhanced (GE) power UMOSFET with split gate (SGE-UMOS) is proposed. This device shows the reduction in specific on-state resistance (R_sp) at a breakdown voltage of 119 V as compared to the gradient oxide-bypassed (GOB) UMOS and GE-UMOS devices, which is due to the higher N-type concentration in the drift region. In addition, the split-gate floating structure in SGE-UMOS also reduces the gate-source electrode parasitic capacitor. The numerical simulation results indicate that the proposed device features high performance with improved R_sp and Qg as compared to that of the GOB-UMOS and GE-UMOS devices.