High-Performance Gate-Enhanced Power UMOSFET With Optimized Structure

Author

Wang, Ying ; Hu, Hai-Fan ; Jiao, Wen-li

Author_Institution

Coll. of Inf. & Commun. Eng., Harbin Eng. Univ., Harbin, China

Volume

31

Issue

11

fYear

2010

Firstpage

1281

Lastpage

1283

Abstract

An optimized gate-enhanced (GE) power UMOSFET with split gate (SGE-UMOS) is proposed. This device shows the reduction in specific on-state resistance (R_sp) at a breakdown voltage of 119 V as compared to the gradient oxide-bypassed (GOB) UMOS and GE-UMOS devices, which is due to the higher N-type concentration in the drift region. In addition, the split-gate floating structure in SGE-UMOS also reduces the gate-source electrode parasitic capacitor. The numerical simulation results indicate that the proposed device features high performance with improved R_sp and Qg as compared to that of the GOB-UMOS and GE-UMOS devices.

Keywords

capacitors; power MOSFET; gate-source electrode parasitic capacitor; gradient oxide-bypassed UMOS; high-performance gate-enhanced power UMOSFET; split gate; split-gate floating structure; voltage 119 V; Capacitors; Electrodes; Electron devices; Fabrication; Logic gates; MOSFET circuits; Materials; Breakdown voltage (BV); gate enhanced (GE); power UMOSFET; specific on-resistance $(R_{rm sp})$; split gate;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2010.2066252

Filename

5560725