Title :
Efficient realisation of MOS-NDR threshold logic gates
Author :
Nunez, Juan ; Avedillo, Maria J. ; Quintana, Jose M.
Author_Institution :
Inst. de Microelectron. de Sevilla (IMSE-CNM-CSIC), Univ. de Sevilla, Sevilla, Spain
fDate :
11/1/2009 12:00:00 AM
Abstract :
A novel realisation of inverted majority gates based on a programmable MOS-NDR device is presented. A comparison, in terms of area and power consumption, has been performed to demonstrate that the proposed circuit is more efficient than a similar reported structure.
Keywords :
MOS integrated circuits; logic gates; MOS-NDR threshold logic gates; area consumption; inverted majority gates; negative differential resistance devices; power consumption;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2009.1651
