DocumentCode :
1310622
Title :
Systolic implementation of higher-order CMAC and its application in colour calibration
Author :
Ker, J.-S. ; Kuo, Y.-H. ; Liu, B.-D.
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Volume :
144
Issue :
3
fYear :
1997
fDate :
6/1/1997 12:00:00 AM
Firstpage :
129
Lastpage :
137
Abstract :
The primary advantages of a CMAC neural network are fast learning and insensitivity to the order in which training patterns are presented. The authors present an extended direct weight cell address mapping mechanism based on a linear systolic array architecture to realise a higher-order CMAC neural network with digital hardware. This higher-order CMAC implementation has been applied to calibrate and compensate the nonlinearity of chromatic mapping between colour scanning and printing devices in a colour image reproduction environment. A 20 MHz prototyped CMAC chip for colour calibration has been implemented to confirm the proposed design approach. Using this prototype, the authors were able to achieve reproduced colour images with rich and vivid colours which strongly resemble the original
Keywords :
CMOS digital integrated circuits; calibration; colour; digital signal processing chips; image restoration; image scanners; neural chips; systolic arrays; 20 MHz; CMAC neural network; CMOS standard cell technology; cerebellar model articulation controller; chromatic mapping; colour calibration; colour image reproduction environment; colour printing devices; colour scanning devices; digital hardware; direct weight cell address mapping mechanism; higher-order CMAC; linear systolic array architecture; prototyped CMAC chip; systolic implementation;
fLanguage :
English
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2409
Type :
jour
DOI :
10.1049/ip-cds:19971005
Filename :
600581
Link To Document :
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