A low hardware cost wear-leveling algorithm for application of smart mobile terminals

NAND flash memory has become a widely-used data storage media. With the scaling down of the cell size, the limited endurance of flash memory is becoming a critical issue. Wear-leveling is employed to evenly distribute program/erase and extend the reliability and lifetime of flash memory. In this paper, a novel wear-leveling algorithm is proposed based on three ideas: firstly, a Block Status Table instead of block erase cycle is constructed to record the status of blocks with lower SRAM consumption; secondly, the heavily worn blocks are screened to involve in garbage collection and free page allocation during dynamic wear-leveling; thirdly, an adjustable threshold is employed to improve the performance of static wear-leveling. Compared to three other state-of-the-art wear-leveling algorithms, the simulation results show that the proposed algorithm features with well wear-leveling performance and larger maximum writable data for five different applications and can reduce the SRAM consumption by 54-60%.