• DocumentCode
    1311033
  • Title

    High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications

  • Author

    Wang, Jiun-Ping ; Kuang, Shiann-Rong ; Liang, Shish-Chang

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Nat. Sun Yat-sen Univ., Kaohsiung, Taiwan
  • Volume
    19
  • Issue
    1
  • fYear
    2011
  • Firstpage
    52
  • Lastpage
    60
  • Abstract
    The fixed-width multiplier is attractive to many multimedia and digital signal processing systems which are desirable to maintain a fixed format and allow a little accuracy loss to output data. This paper presents the design of high-accuracy fixed-width modified Booth multipliers. To reduce the truncation error, we first slightly modify the partial product matrix of Booth multiplication and then derive an effective error compensation function that makes the error distribution be more symmetric to and centralized in the error equal to zero, leading the fixed-width modified Booth multiplier to very small mean and mean-square errors. In addition, a simple compensation circuit mainly composed of the simplified sorting network is also proposed. Compared to the previous circuits, the proposed error compensation circuit can achieve a tiny mean error and a significant reduction in mean-square error (e.g., at least 12.3% reduction for the 16-bit fixed-width multiplier) while maintaining the approximate hardware overhead. Furthermore, experimental results on two real-life applications also demonstrate that the proposed fixed-width multipliers can improve the average peak signal-to-noise ratio of output images by at least 2.0 dB and 1.1 dB, respectively.
  • Keywords
    error compensation; mean square error methods; multiplying circuits; average peak signal-to-noise ratio; digital signal processing systems; error compensation circuit; error distribution; high-accuracy fixed-width modified booth multipliers; mean-square errors; multimedia systems; sorting network; truncation error reduction; Adders; Circuits; Digital signal processing; Error compensation; Finite wordlength effects; Hardware; Multimedia systems; PSNR; Sorting; Symmetric matrices; Error compensation circuit; fixed-width multiplier; mean error; mean-square error; modified Booth multiplier;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2009.2032289
  • Filename
    5325646