Split-Gate-Enhanced UMOSFET With an Optimized Layout of Trench Surrounding Mesa

An optimized split-gate-enhanced UMOSFET (SGE-UMOS) layout design is proposed, and its mechanism is investigated by 2-D and 3-D simulations. The layout features trench surrounding mesa (TSM): First, it optimizes the distribution of electric field density in the outer active mesa, reduces the electric-field crowding effect, and improves the breakdown voltage of the SGE-UMOS device. Second, it is unnecessary to design the layout corner with a large diameter in the termination region for the TSM structure as the conventional mesa surrounding trench (MST) structure, which is more efficient in terms of silicon usage. R_sp.on is reduced when compared with the MST structure within the same rectangular chip area. The BV of SGE-UMOS is increased from 72 to 115 V, and R_sp.on is reduced by approximately 3.5% as compared with the MST structure, due to the application of the TSM. Finally, it needs five masks in the process, and the trenches in active and termination regions are formed with the same processing steps; hence, the manufacturing process is simplified, and the cost is reduced as well.