Title :
Digital lock-detection for systematic phase noise elimination in a phase interpolator CDR
Author :
Ardalan, S. ; Yu Feng
Author_Institution :
Dept. of Electr. Eng., Center for Analog & Mixed Signals, San Jose State Univ. San Jose, San Jose, CA, USA
Abstract :
A novel solution to eliminating the systematic phase noise in a phase interpolator (PI) clock-to-data recovery (CDR) system was designed and simulated in Simulink. The proposed solution addresses the systematic jitter caused by the bang-bang phase detector using scalable digital logic.
Keywords :
clock and data recovery circuits; interpolation; jitter; logic devices; phase detectors; phase noise; PI clock-to-data recovery; Simulink; bang-bang phase detector; digital lock-detection; phase interpolator CDR; scalable digital logic; systematic jitter; systematic phase noise elimination; Clocks; Detectors; Jitter; Mixers; Phase locked loops; Radiation detectors; Systematics;
Conference_Titel :
New Circuits and Systems Conference (NEWCAS), 2014 IEEE 12th International
Conference_Location :
Trois-Rivieres, QC
DOI :
10.1109/NEWCAS.2014.6933994
