Efficient address generation for prime factor algorithms [digital signal processing]

An attempt is made to explain as clearly as possible the problem of address generation and how the prime factor mapping technique is used in this class of algorithms. Two novel address generation schemes are proposed to improve efficiency. The first scheme reduces the computation required for unscrambling data in an in-place realization of the PFA (prime factor algorithm) by reducing the number of variables used to calculate the data addresses. The second scheme is to be used in an in-place in-order realization of PFA. It achieves high efficiency by replacing complicated modulo operations of conventional approaches by simple indirect addressing techniques. Making use of this scheme, software packages have been written for the computation of DFTs (discrete Fourier transforms) using a high-level language and two low-level languages (the 80286/287 and TMS330C25 assembly languages). Results of these realizations show that a reduction of 50% in address generation time is achievable, giving a saving of 30% in total computation time. A hardware address generator is also developed, which may provide clues to improving digital signal processor architectures in the future