Energy and accuracy in multi-stage stochastic computing

The continued scaling of feature sizes in integrated circuit technology leads to more uncertainty and unreliability in circuit behaviour. Maintaining the paradigm of deterministic Boolean computing therefore becomes increasingly challenging. Stochastic computing (SC) processes digital data in the form of pseudo-random bit-streams denoting probabilities and is therefore less vulnerable to uncertainty. When transient circuit variations are present, SC greatly outperforms classical binary implementations. Previous work has mainly been on SC circuits with only a few stages. This paper assesses the feasibility of multistage SC. First the reasons for decreasing accuracy in these types of circuits are discussed. Second, we introduce a straightforward method to evaluate the accuracy of general SC systems. Third, the validity of this new approach is illustrated through the design of a 1D-DCT stochastic circuit, as part of a JPEG compression accelerator. Last, we couple the results of our analysis to low-level energy considerations.