DocumentCode :
1313109
Title :
Prefetch-Aware Memory Controllers
Author :
Lee, Chang Joo ; Mutlu, Onur ; Narasiman, Veynu ; Patt, Yale N.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA
Volume :
60
Issue :
10
fYear :
2011
Firstpage :
1406
Lastpage :
1430
Abstract :
Existing DRAM controllers employ rigid, nonadaptive scheduling and buffer management policies when servicing prefetch requests. Some controllers treat prefetches the same as demand requests, and others always prioritize demands over prefetches. However, none of these rigid policies result in the best performance because they do not take into account the usefulness of prefetches. If prefetches are useless, treating prefetches and demands equally can lead to significant performance loss and extra bandwidth consumption. In contrast, if prefetches are useful, prioritizing demands over prefetches can hurt performance by reducing DRAM throughput and delaying the service of useful requests. This paper proposes a new low hardware cost memory controller, called as Prefetch-Aware DRAM Controller (PADC), that aims to maximize the benefit of useful prefetches and minimize the harm caused by useless prefetches. The key idea is to 1) adaptively prioritize between demands and prefetches, and 2) drop useless prefetches to free up memory system resources, based on prefetch accuracy. Our evaluation shows that PADC significantly outperforms previous memory controllers with rigid prefetch handling policies. Across a wide range of multiprogrammed SPEC CPU 2000/2006 workloads, it improves system performance by 8.2 and 9.9 percent on four and eight-core systems while reducing DRAM bandwidth consumption by 10.7 and 9.4 percent, respectively.
Keywords :
DRAM chips; scheduling; storage management; DRAM controller; SPEC CPU 2000 workload; SPEC CPU 2006 workload; buffer management policy; dynamic random access memory; prefetch-aware DRAM controller; prefetch-aware memory controller; scheduling policy; Bandwidth; Hardware; Prefetching; Processor scheduling; Random access memory; System performance; Throughput; DRAM; Memory systems; memory controllers; multi-core systems.; prefetching;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2010.214
Filename :
6008537
Link To Document :
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