Device-circuit co-design and comparison of ultra-low voltage Tunnel-FET and CMOS digital circuits

Author

Esseni, David ; Alioto, Massimo

Author_Institution

DIEGM, Univ. of Udine, Udine, Italy

fYear

2014

fDate

22-25 June 2014

Firstpage

321

Lastpage

324

Abstract

This paper presents a comparative study between Tunnel-FETs (TFETs) and SOI MOSFETs for ultra-low power digital circuits targeting ultra-low voltages (below 500mV). We illustrateg a device-circuit co-design of n- and p-type Tunnel FETs leading to a good tradeoff between current leakage, effective capacitance and transistor imbalance at ultra-low V_DD. TFETs and MOSFETs at 30 nm gate length are compared in terms of DC robustness, effect of transistor stacking, performance and potential for minimum-energy operation under aggressive voltage scaling.

Keywords

CMOS digital integrated circuits; MOSFET; integrated circuit design; leakage currents; low-power electronics; semiconductor device models; tunnel transistors; CMOS digital circuits; DC robustness; SOI MOSFET; Si; aggressive voltage scaling; current leakage; device-circuit co-design; effective capacitance; minimum-energy operation; n-tunnel FET; p-type tunnel FET; size 30 nm; transistor imbalance; transistor stacking effect; ultra-low power digital circuits; ultra-low voltage tunnel-FET; Capacitance; Doping; Logic gates; MOSFET; Robustness; Device-circuit co-design; VLSI; tunnel FET; ultra-low power; ultra-low voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

New Circuits and Systems Conference (NEWCAS), 2014 IEEE 12th International

Conference_Location

Trois-Rivieres, QC

Type

conf

DOI

10.1109/NEWCAS.2014.6934047

Filename

6934047