Towards nano-computing blocks using room temperature double-gate single electron transistors

Author

Bounouar, Mohamed Amine ; Drouin, Dominique ; Calmon, Francis

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. de Sherbrooke, Sherbrooke, QC, Canada

fYear

2014

fDate

22-25 June 2014

Firstpage

325

Lastpage

328

Abstract

This paper explore the potential and the use of room temperature Double-Gate Single Electron Transistor (DG-SET) in digital logic circuits. For this purpose, we exploit the double gate nature of DG-SET nano-devices. Full-custom design of elementary blocks based on DG-SET such as SRAM, Arithmetic Logic Unit (ALU) and Look-Up Table (LUT) are presented. Evaluation of the performances metrics is done in order to highlight the benefit of DG-SET in future ULSI.

Keywords

ULSI; logic circuits; single electron transistors; ALU; DG-SET nanodevices; LUT; SRAM; ULSI; arithmetic logic unit; digital logic circuits; double-gate single electron transistors; elementary blocks; full-custom design; look-up table; nanocomputing blocks; performances metrics; temperature 293 K to 298 K; CMOS integrated circuits; Logic gates; Random access memory; Single electron transistors; Table lookup; Transistors; ALU; Double-Gate Single Electron Transistor (DG-SET); LUT; Low-power; Nano-circuits; Room Temperature; building blocks;

fLanguage

English

Publisher

ieee

Conference_Titel

New Circuits and Systems Conference (NEWCAS), 2014 IEEE 12th International

Conference_Location

Trois-Rivieres, QC

Type

conf

DOI

10.1109/NEWCAS.2014.6934048

Filename

6934048