DocumentCode
1313507
Title
Carry-save adders for computing the product AB modulo N
Author
Koc, C.K. ; Hung, C.Y.
Author_Institution
Dept. of Electr. Eng., Houston Univ., TX, USA
Volume
26
Issue
13
fYear
1990
fDate
6/21/1990 12:00:00 AM
Firstpage
899
Lastpage
900
Abstract
The authors describe a new algorithm for modulator multiplication using carry-save adders. The proposed algorithm is based on the sign-estimation technique. A carry-save adder structure consisting of three rows of n+3 simple 1-bit adder cells, and two copies of 3-bit carry look-ahead logic can be used to implement a single step of the algorithm. A completely pipelined array for modular multiplication designed by cascading n carry-save adders performs modulator multiplication at the clock rate.
Keywords
adders; carry logic; digital arithmetic; multiplying circuits; pipeline processing; carry look-ahead logic; carry-save adders; modulator multiplication; pipelined array; sign-estimation technique;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19900587
Filename
82835
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