Title :
Sub-1 V, 4 na CMOS voltage references with digitally-trimmable temperature coefficient
Author :
Luong, Peter ; Christoffersen, Carlos ; Rossi-Aicardi, Conrado ; Dualibe, Carlos
Author_Institution :
Dept. of Electr. Eng., Lakehead Univ. Thunder Bay, Thunder Bay, ON, Canada
Abstract :
Two architectures for MOS-only low power voltage references with digitally-trimmable temperature coefficient are proposed in this work. A test chip implements them in a 0.35 μm CMOS process. A design methodology for both architectures, performance figures and preliminary test results are presented. Each circuit consumes around 4 nA and operates down to 0.95 V or better with a simulated temperature coefficient of 18 ppm/° C in the -20°C to 80°C range.
Keywords :
CMOS digital integrated circuits; low-power electronics; reference circuits; CMOS voltage references; MOS-only low power voltage references; current 4 nA; design methodology; digitally-trimmable temperature coefficient; performance figures; preliminary test results; size 0.35 mum; temperature -20 degC to 80 degC; test chip; CMOS integrated circuits; MOSFET; Temperature distribution; Temperature measurement; Threshold voltage;
Conference_Titel :
New Circuits and Systems Conference (NEWCAS), 2014 IEEE 12th International
Conference_Location :
Trois-Rivieres, QC
DOI :
10.1109/NEWCAS.2014.6934053
