DocumentCode
131383
Title
The P/DLL frequency synthesizer architecture: A native trade-off between stability and wideband frequency generation
Author
Deval, Yann ; de Peslouan, P.-O Lucas ; Taris, T. ; De Matos, Magali ; Belot, Didier
Author_Institution
IMS Lab., Univ. of Bordeaux, Talence, France
fYear
2014
fDate
22-25 June 2014
Firstpage
413
Lastpage
416
Abstract
A new technique for the stabilization of local oscillators by the way of frequency synthesis is presented. A combination of both a PLL and a DLL in a novel frequency synthesizer architecture overcomes the drawback of PLL stability, while avoiding the classical DLL out-of-band spurious. Therefore, the Mixed P/DLL synthesizer can exhibit very wideband and, consequently, can dramatically reduce the local oscillator phase noise and the synthesizer settling time. Dynamic performances of an unstable PLL are then observed, while the system stability is guaranteed by the DLL first order loop behavior. A 130nm CMOS experimental demonstrator is presented, able to synthetize local oscillator form 1 to 3.5GHz, with settling time as low as 1.2μs.
Keywords
CMOS analogue integrated circuits; MMIC oscillators; UHF integrated circuits; UHF oscillators; circuit stability; delay lock loops; field effect MMIC; frequency synthesizers; microwave oscillators; phase locked loops; phase noise; CMOS experimental demonstrator; DLL first order loop behavior; DLL out-of-band spurious; PLL stability; frequency 1 GHz to 3.5 GHz; local oscillator phase noise; local oscillator stabilization; mixed P/DLL frequency synthesizer architecture; size 130 nm; system stability; unstable PLL dynamic performances; wideband frequency generation; Delays; Frequency synthesizers; Local oscillators; Phase locked loops; Phase noise; Synthesizers; Wideband;
fLanguage
English
Publisher
ieee
Conference_Titel
New Circuits and Systems Conference (NEWCAS), 2014 IEEE 12th International
Conference_Location
Trois-Rivieres, QC
Type
conf
DOI
10.1109/NEWCAS.2014.6934070
Filename
6934070
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