VCO design in SOI technologies

In this paper, we present the design of 2 PLL for low power Bluetooth applications, one in 130 nm PDSOI and the other in 28 nm FDSOI technologies. The PDSOI one is based on a classical LC tank VCO and uses the possibility of body contact to modulate the current core of the VCO in order to decrease the phase noise. Good performances in terms of phase noise are achieved with this technique, but we do not gain any size nor power consumption compared to a more classical bulk solution. This LC tank VCO is mandatory for such telecommunication applications. We propose to use a ring oscillator VCO to build a PLL in FDSOI technology. Despite the fact that such VCO topology exhibits a larger phase noise, this design will address aggressively the size and power consumption reduction. Indeed we are using the efficient backgate biasing offered by the FDSOI MOS transistor to compensate the mismatches between the different inverters of the ring oscillator to decrease jitter and phase noise.