Title :
Timing optimization on routed designs with incremental placement and routing characterization
Author :
Changfan, Chieh ; Hsu, Yu-Chin ; Tsai, Fur-Shing
Author_Institution :
Dept. of Comput. Sci., California Univ., Riverside, CA, USA
fDate :
2/1/2000 12:00:00 AM
Abstract :
Wire delay estimation has been a problem in designs of very deep submicron (VDSM) technologies with feature size under 0.25 μm. The conventional back-annotation approach does not guarantee timing convergence due to different estimation techniques for prelayout and post-layout timing. In this paper, a post-routing timing optimization algorithm is presented. Experimental results show that this algorithm provides better result after detail routing is completed
Keywords :
capacitance; circuit layout CAD; circuit optimisation; delay estimation; integrated circuit layout; network routing; timing; incremental placement; post-routing optimization algorithm; routed designs; routing characterization; timing convergence; timing optimization; very deep submicron technologies; wire delay estimation; Convergence; Delay estimation; Design optimization; Logic; Optimization methods; Parasitic capacitance; Routing; Timing; Very large scale integration; Wire;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
