Gain and sensitivity as design criteria for iterative transistor amplifiers

A procedure is developed which permits the design of iterative stages for a transistor amplifier required to satisfy specified gain, gain sensitivity, and d-c stabilization criteria. After initial imposition of the circuit constraints necessary to insure acceptable operating point stability, the designer may proceed to examine the limits of achievable gain and gain sensitivity; then he is in a position to compromise such conflicting requirements as may have been exposed or to select a transistor with greater performance capability. The design is completed by means of an orderly sequence of calculations.