DocumentCode
1315298
Title
10 Gbit/s bit interleaving CDR for low-power PON
Author
Van Praet, C. ; Torfs, G. ; Li, Zuyi ; Yin, X. ; Suvakovic, Dusan ; Chow, Hungkei ; Qiu, Xing-Zhi ; Vetter, Peter
Volume
48
Issue
21
fYear
2012
Firstpage
1361
Lastpage
1363
Abstract
A novel, low power, downstream clock and data recovery (CDR)-decimator architecture is proposed for next generation, energy efficient 10 Gbit/s optical network units (ONUs). The architecture employs a new time division multiplexing bit-interleaving downstream concept for passive optical networks (Bi-PON) allowing early decimation of the incoming data and lowering of the processing speed to the user rate of the ONU, thus reducing the power consumption significantly.
Keywords
low-power electronics; passive optical networks; time division multiplexing; bit interleaving CDR; bit rate 10 Gbit/s; data recovery; decimator architecture; downstream clock recovery; energy efficient optical network units; low-power PON; passive optical networks; power consumption; processing speed; time division multiplexing bit-interleaving downstream concept; user rate;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el.2012.3200
Filename
6329308
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