Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node Upset

The occurrence of a single event with a multiple-node upset is likely to increase significantly in nanoscale CMOS due to reduced device size and power supply voltage scaling. This paper presents a comprehensive treatment (model, analysis, and design) for hardening storage elements (memories and latches) against a soft error resulting in a multiple-node upset at 32-nm feature size in CMOS. A novel 13T memory cell configuration is proposed, analyzed, and simulated to show a better tolerance to the likely multiple-node upset. The proposed hardened memory cell utilizes a Schmitt trigger (ST) design. As evidenced in past technical literature and used in this work, simulation of all node pairs by current sources results in an assessment similar to 3-D device tools; the simulation results show that the proposed 13T improves substantially over DICE in the likely and realistic scenarios of very diffused or limited charge sharing/collection. Moreover, the 13T cell achieves a 33% reduction in write delay and only a 5% (9%) increase in power consumption (layout area) compared to the DICE cell (consisting of 12 transistors). The analysis is also extended to hardened latches; it is shown that the latch with the highest critical charge has also the best tolerance to a multiple-node upset. Among the hardened latches, the ST designs have the best tolerance, and in particular, the transmission gate configuration is shown to be the most effective. Simulation results are provided using the predictive technology file for 32-nm feature size in CMOS. Monte Carlo simulation confirms the excellent multiple-node upset tolerance of the proposed hardened storage elements in the presence of process, voltage, and temperature variations in their designs.