DocumentCode
1316276
Title
Run-Time Reconfiguration of Expandable Cache for Embedded Systems
Author
Hsieh, Ang-Chih ; Hwang, Ting Ting
Author_Institution
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume
20
Issue
10
fYear
2012
Firstpage
1863
Lastpage
1875
Abstract
Expandable cache proposed by Bournoutian and Orailoglu is very efficient in reducing miss rate and energy consumption with small area overhead. However, the original expandable cache with only one expansion scheme may lead to thrashing problems. In this work, based on the structure of expandable cache, we will introduce a new cache design which has many expansion schemes to fit different run-time program behaviors. The expansion scheme of our proposed cache is dynamically changed by executing configuration instructions which are inserted at compile time. The experimental results of SPEC CPU2000 have shown that our proposed cache design effectively improves the miss rate by 14.74% as compared with the original expandable cache. In terms of energy improvement ratio, our method is 5.62% higher than that of expandable cache when the baseline is set as the energy consumption of 2-way set-associative cache.
Keywords
cache storage; embedded systems; energy consumption; memory architecture; power aware computing; SPEC CPU2000; cache design; compile time; configuration instruction execution; embedded systems; energy consumption reduction; expandable cache; expansion scheme; miss rate reduction; run-time program behavior; run-time reconfiguration; thrashing problems; Cache storage; Embedded systems; Energy consumption; Memory architecture; Power demand; Program processors; Cache storage; embedded systems; memory architecture; power efficiency;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2011.2163534
Filename
6012499
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