Title :
On the Analysis of Fault Trees
Author_Institution :
Department of Electronics//The University//Southampton S09 5NH ENGLAND
Abstract :
The paper is concerned with the analysis of fault trees and describes an algorithm for deriving a reduced Boolean sum-of-product (s-o-p) expression from a description of the structure. The algorithm was developed initially as an analytic procedure for combinational logic networks and employs a reverse Polish notation to describe the structure which is then converted to an equivalent s-o-p expression. This procedure is equally applicable to fault tree analysis but care must be exercised in interpreting the Boolean result as a probability relationship. This aspect is discussed and a simple test and modification procedure described, enabling the original Boolean s-o-p expression to be converted into an equivalent s-o-p expression which can be interpreted directly as a probability relationship.
Keywords :
Algorithm design and analysis; Boolean algebra; Boolean functions; Computer networks; Fault trees; Logic testing; Network topology; Power supplies; Set theory; Switches;
Journal_Title :
Reliability, IEEE Transactions on
DOI :
10.1109/TR.1975.5215143