Title :
Efficient test generation algorithm for path delay faults
Author :
Kim, Myoung-Gym ; Kang, Sungho
Author_Institution :
Dept. of Electr. Eng., Yonsei Univ., Seoul, South Korea
fDate :
1/6/2000 12:00:00 AM
Abstract :
A new algorithm has been developed to perform efficient delay testing. The algorithm enables applications of a new implication of value using indirect implication. The results of ISCAS benchmark circuits show the effectiveness of the new algorithm
Keywords :
VLSI; automatic testing; delays; fault diagnosis; integrated circuit testing; logic testing; ISCAS benchmark circuits; VLSI; delay testing; indirect implication; logic testing; path delay faults; test generation algorithm;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20000043
